AXI or Avalon MM

Both buses are need !

All Altera-s IP-cores maked with Avalon historical, and AXI is base in ARM processor and linking all peripheral to it.

May be adapters AXI-Avalon and back, even in examples, search !

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In the documention they say you can choice either for AXI or Avalon-MM. I tend to go for the AXI bus because this way i don't have to translate the Avalon-MM to AXI interface and the complition signal is also usefull.

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Qsys will insert adapter logic, so the need for conversion is less of a concern.

Personally I would base the decision on which interface is well-supported by Altera's verification suite. Up until recently, only the Avalon-MM interfaces had decent verification support, i.e., BFMs. Altera does have support for AXI, but its via Mentor Graphics BFMs. I have not tested the AXI BFMs.

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And connected to this question. I want to connect my own FPGA blocks with Port map ( A => B ), Not using Qsys, (because Qsys automatically uses Avalon) to the AXI interface. would this be even possible ?

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Yes, its trivial. I have a number of designs with a single Avalon-MM master (based on an FTDI USB-to-FIFO bridge) and one or a few slaves (RAM + registers) and for testing I just connect those directly together.

However, its also easy to connect them with Qsys. The generated code is easy to read, so you can open up the top-level file and check that the Qsys system matches what you expect.

Cheers,

Dave

Thnx, really helpful comment.

Is there any reason why one should want to use AXI within FPGA fabric, apart from your IP is AXI or your customer wants it ? Because i'm trying to figure out the pro's and con's of having AXI or Avalon.

thanks in advanced.

Cheers,

Hidde

Hi Hidde,

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Is there any reason why one should want to use AXI within FPGA fabric, apart from your IP is AXI or your customer wants it ? Because i'm trying to figure out the pro's and con's of having AXI or Avalon.

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It comes down to what you want to use the code you develop for. If I was writing code to target Altera and Xilinx devices, then I would create AXI components. If the code is specific to an Altera design, and I care more about ease of verification, then I'd write Avalon components.

You should apply the same philosophy as coding-style, i.e., use a style that matches the project code-base. In your case, if your Qsys system contains a lot of Avalon-MM components, then write the new components with Avalon-MM interfaces too. It will make the long-term maintenance of the code (potentially) easier (due to the common bus standard used in the code).

Cheers,

Dave

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We have decided to use avalon as standard bus.

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Great!

For examples of the Avalon-MM Verification IP, see these threads;

http://www.alteraforum.com/forum/sho...t=32952&page=3

http://www.alterawiki.com/wiki/using_the_usb-blaster_as_an_sopc/qsys_avalon-mm_master_tutorial

http://www.alteraforum.com/forum/showthread.php?t=34787

Cheers,

Dave