Average in VHDL..?

I am not quite sure of VHDL.

in case verilog HDL.

you can just write as like software calculation.

such as...

avg <= sumdata / sumnum;

or

you can just use div megacore function.

notice that.

in both way.

you need to pay attention for timing delay.

it might take few clocks.depending on FPGA and bit width.

I hope this information helps you.

see you.