Honored Contributor
Honored ContributorHello OmniKing,
I mean that if you recompile DDR3 IP it generates files. In which files the top file you need to open and delete all "_vector(0 downto 0)". In my configuration I have 4 chips in unbuffered dimm and IP generates for some signals not std_logic but std_logic_vector(0 downto 0). And if you run *.tcl for constraints you will have errors until you rename signals from std_logic_vector(0 downto 0) to std_logic. This mistake is allready talked in other forum threads. It seems to me that all others work with DDR3 IP together with SOPC or Qsys. For my projects I don't need this systems, I never worked with them and I don't have time to learn them. Now I use altmemphy IP for DDR3, and it works well without any SOPC or Qsys. I created 4 (four) different DDR3 IPs without any problem. Althougth Altera sugessts to use UniPhy becouse it has some debug things. Yes, I saw that debug things allrigth work but IP don't work correctly. I tried in Quartus versions from 10.1 to 13, and in every versions IP doesn't work differently :). Probably I don't understand something and don't see my mistakes, but nobody answer me that it's true :). GoodLuck, if you find out something, please write me! Best wishes, Anton
