Avalon wrapper for altfp_matrix_mult?

I have not done this but it should be possible.

I would probably build a read master frontend to fetch the A and B matrix elements from memory and then put a write master backend to write the results back to memory. The megafunction would sit in between the read and write masters.

Alternatively you could use DMAs for this and put some logic between the DMA and the megafunction to re-format the data entering/leaving the megafunction.

I personally think just building in your own read and write masters would be the better method since it'll be tuned for what you are trying to do. It'll be more work as well but if you are looking for high performance this is the price to pay.

What would be a good approach for writing such a master? How would the NIOS CPU be able to control the data flow? Let me explain what I am trying to do. Basically I have an FFT component that is going to process tons of data. However, the output of each FFT needs to be multiplied by some other constants, and perhaps from another FFT's output. This leads me to believe that the altft_matrix_mult component would be useful- but I wonder how NIOS could orchestate it.

This is what I am thinking :

1. Build a FSM that controls the enable signal, loada, and loadb signals, based upon the status of a FIFO that holds the data from the FFT (lots of unknowns here...).

2. When the FIFO is almost full (whatever the almost_full parameter is...maybe half full??), begin to pop the FIFO and enable the loada signal until 4096 FFT results are loaded to the multiplier.

3. Repeat step 2, to load the other input, b, for 4096 values.

4. Enable the core, wait for done, and feed outputs into another FIFO.

5. Have NIOS read from the FIFO and store into memory locations for output to terminal.

Currently I am doing all of the multiplications in software and it is costing WAY TOO MANY cycles. Would this be a good approach? Any suggestions or cautionary notes?

Thanks

When I build masters at a high level I do this:

1) Always build in a FIFO to ensure high performance

2) Always de-couple the command logic (addressing, read/write, etc...) from the data logic (writedata, readdata, readdatavalid).... this is easy if you do# 1

3) Exclude bursting if possible since that just adds additional complexity to the control logic.

Based on your description it might make more sense to put a streaming frontend on altft_matrix_mult and just stream the data in and out of it. Internally your component would address the memory locations of the altft_matrix_mult to stuff the matrix memories with the input content. If the "B" matrix is constant then maybe you can prepopulate it by attaching a slave port to it and have Nios II write the contents in the first time. If you want to get the data back out you could use a DMA to pull the contents out and write it to memory.

Have a look at this DMA, it may give you some ideas of what to do: http://www.altera.com/support/examples/nios2/exm-modular-scatter-gather-dma.html?gsa_pos=1&wt.oss_r=1&wt.oss=sgdma