Avalon wrapper for altfp_matrix_mult?

What would be a good approach for writing such a master? How would the NIOS CPU be able to control the data flow? Let me explain what I am trying to do. Basically I have an FFT component that is going to process tons of data. However, the output of each FFT needs to be multiplied by some other constants, and perhaps from another FFT's output. This leads me to believe that the altft_matrix_mult component would be useful- but I wonder how NIOS could orchestate it.

This is what I am thinking :

1. Build a FSM that controls the enable signal, loada, and loadb signals, based upon the status of a FIFO that holds the data from the FFT (lots of unknowns here...).

2. When the FIFO is almost full (whatever the almost_full parameter is...maybe half full??), begin to pop the FIFO and enable the loada signal until 4096 FFT results are loaded to the multiplier.

3. Repeat step 2, to load the other input, b, for 4096 values.

4. Enable the core, wait for done, and feed outputs into another FIFO.

5. Have NIOS read from the FIFO and store into memory locations for output to terminal.

Currently I am doing all of the multiplications in software and it is costing WAY TOO MANY cycles. Would this be a good approach? Any suggestions or cautionary notes?

Thanks