Avalon interface

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hi all,

I m a newbie to FPGA. Can anyone tell me what is an avalon interface?

any Links and documents will also be sufficient.

Thanks and Regards,

Iyan

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Avalon is Altera's interface protocol, link to the spcification is here

http://www.altera.com/literature/manual/mnl_avalon_spec.pdf?gsa_pos=1&wt.oss_r=1&wt.oss=avalon manual

Although technically a proprietary interface, it is very similar in nature to open interfaces such as Wishbone. The heart of Avalon can easily be understood with the following simple concepts:

Transaction: Either a 'read' or a 'write'

Master: The master initiates a transaction

Slave (or Target to be PC): The slave responds to transactions initiated by the master

The basic signals are:

read: Initiated by the master, responded to by the slave

readdata: Driven by the slave in response to a read command

write: Initiated by the master, responded to by the slave

writedata: Driven by the master along with the write command

waitrequest: Driven by the slave to indicate that the master needs to maintain the current command while the read or write completes. If the slave can always complete the command on one clock cycle, then waitrequest would always be 0.

Altera divides Avalon into 'memory mapped' and 'streaming' interaces, but the differences are mostly cosmetic. It's still a useful separation, but the basic idea in both cases is the same: the slave presents status to indicate whether it is ready to complete a command, the master generates the commands. Streaming interfaces introduce new terminology such as 'source' and 'sink' to indicate where data starts from and where it ends up, but that distinction is not fundamentally any different than 'master/slave'. One or the other might stick better in your mind though and therefore be easier to learn.

A widget of some source can have multiple interfaces. For example, if you have some code that implements an image processing algorithm, you might have three interfaces:

- One to setup the image processing parameters. Typically this would be a memory mapped interface that is connected in some fashion to a processor

- One to receive the input data. This could be either streaming or memory mapped depending on the thing that you intend to interface with.

- One to output the data. Again this could be either streaming or memory mapped.

The basic concept is that standardizing on a protocol for transferring data decouples basic code (such as the image processing algorithm) from external concerns (like peculiarities of a camera interface). This promotes code reuse so you don't keep re-inventing the wheel.

Kevin Jennings