Forum Discussion
Altera_Forum
Honored Contributor
7 years agoFPGA synthesis never implements any resource that isn't "actually used". I guess the problem is that you don't understand which part of the code infers a RAM based shift register. But without seeing the code, it's hard to tell.
The hierarchy view already tells you that it's used in the implementation of dataodd_rtl. There's no additional autogenerated logic, it's just the way how altshift_taps is implemented.