Asynchronous v. Synchronous Logic

Using edge sensitive always blocks trigerred by nRD or nWR isn't asynchronous logic. It's synchronous using multiple clock domains. In this case, the problems are brought up by transfering data or state information between clock domains.

As you say the clock frequency is low, synchronous edge detection in a single clock domain should however work well. It's the preferred method to interface synchronous logic e.g. with an asynchronous data bus, provided the system clock can keep up with the bus speed. It usually works when all involved control signals are wider than a clock cycle.

ALE can be usually processed with a separate address latch.