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Honored Contributor
Honored ContributorAsynchronous v. Synchronous Logic
Am (still) relatively new to FPGA development. Please bear with me. Am using an FPGA to monitor address/data lines on an old (very old) MPU. I need to capture when an address is asserted on t...
Altera_ForumHonored Contributor
Honored ContributorSo your synchronous event for a write is the rising edge of WRn.
Your read *data* can be generated asynchronously from the address without qualification or synchronously from the falling edge of the ALE (either of which could ba gated downstream by the RDn). Any FIFO read counters would be updated synchronously from the rising edge of the RDn. You should be able to get everything you need with very clean synchronous design. - John
