ASx4 Interface debug in MSEL=111 (JTAG mode)

Hi Frank,

thank you. Unfortunately looks like this. I also did not find any explicit mention. Nevertheless I would appreciate from Altera when there would be a warning message in the console log (at least) that I am trying to do something not supported. Since having SDM I found no way of testing the memory connection over JTAG when something is wrong. In the BSDL file there are no IO buffers defined for the SDM_IOxx either.

What was by the way a strange thing in the AN995 that it was mentioning that I have the ASx4 debugging available when the FPGA programmed with an active serial x4 enabled image. So the question is that setting also part of the SRAM image I am programming? does the FPGA know that the .sof image I program supposed to be read normally from NOR over ASx4?

Or it is more related to the MSEL inputs only and nothing else.

Thanks,

Peter