Honored ContributorHi,
yes I have defined a clock for "clk", as you see in the picture. I have another project with the same settings and it works. Don't know what is wrong. Maybe someone had the same issue and got it solved? I use Quartus 8.1
Honored ContributorI'm sorry, it's solved:
under ..\More Timing Settings\Ignore Clock Settings should be set to OFF !!Honored Contributori'm using Quartus II . How to solve this issue. I don't have this More settings available. I'm attaching a screen short along with this.
Honored ContributorThe original post was using classic timing analyser that is no longer available.
You need to write an SDC file that defines all of the timings for the designHonored ContributorSorry i don't know how to write an SDC. is there any other way we could solve this... ? or could you please give me a small SDC eg. ?
Honored ContributorYou need to write an SDC file to constrain your design. At a minimum it defines the clock, but also things like false paths, multicycle paths, IO delays etc.. Read this tutorial here:
https://www.altera.com/en_us/pdfs/literature/ug/ug_tq_tutorial.pdf
