Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAssuming node "clk" is an undefined clock
Hi,
yes I have defined a clock for "clk", as you see in the picture. I have another project with the same settings and it works. Don't know what is wrong. Maybe someone had the same issue and got it solved? I use Quartus 8.15 Replies
Altera_ForumI'm sorry, it's solved:
under ..\More Timing Settings\Ignore Clock Settings should be set to OFF !!- Altera_Forum
i'm using Quartus II . How to solve this issue. I don't have this More settings available. I'm attaching a screen short along with this.
- Altera_Forum
The original post was using classic timing analyser that is no longer available.
You need to write an SDC file that defines all of the timings for the design - Altera_Forum
Sorry i don't know how to write an SDC. is there any other way we could solve this... ? or could you please give me a small SDC eg. ?
- Altera_Forum
You need to write an SDC file to constrain your design. At a minimum it defines the clock, but also things like false paths, multicycle paths, IO delays etc.. Read this tutorial here:
https://www.altera.com/en_us/pdfs/literature/ug/ug_tq_tutorial.pdf
