Assembling an FPGA board on 2 layers PCB

If you put a lot of care and work into the design layout you could get it working on a 2 layer PCB (I'm going to catch a lot of flak for saying this).

But at the price of 4-layer boards nowadays I would use a 4-layer design. It will make life easy, especially as you are receiving data at a 100 MHz rate from an ADC. Do not forget that all those fast outputs need well terminated/designed transmission lines unless the distance traveled is less than 15 mm (what you will not be able to achieve on a 2-layer board).

what is possible depends upon what the target is specified for

i would say that 100MHz is a no go, as 100MHz is not a rectangular but sinusiodal 1. frequency of or clock. so your 100MHz will need the 3. and at minimum the 5. harmonic so you get 300MHz and 500MHz as well. to handle that with a 2 layer pcb .. no further comment

okay i knew of designs running sdram at 100MHz on a 2 layer pcb but i wouldn#T do that.

go for at least 4 layer pcb, that will enable you to provide low impedance |Z| of you power supply

(Shot no. 1)

Thinking a bit further on it.

I guess there are about 18 signals between the FPGA and the ADC and I guess about the same amount between the FPGA and the USB device, so we can connect each device to one side of the FPGA, leaving 2 sides totally free. (adding the configuration device and possibly a JTAG port may/will complicate things a bit)

The bottom side covered with gnd, except for a square under the FPGA which carries VccInt.

On the top layer we have a square (or 2 rectangles) under the FPGA to carry VccIO(s). All the signals are routed on the top layer, possible with gnd traces between them (at least for the clocks).

Using series termination to terminate the signal connections. (Unless we can keep the connections under 15mm)

The power supplies are routed in copper pour on the top layer as well.

Sprinkle a lot of capacitors (10µF, 100nF, 1nF) to decouple the power supplies.

Handling higher frequencies has to do with properly designing the transmission lines, not with the number of layers used. Also it is not really frequency that matters but the rise time of the signals. E.g, a 100 MHz clock and a 1HZ clock produce by a StratixII FPGA both have a rise time of 800 ps or so ...

But I totally agree it will be a lot quicker to design it / lay it out on a 4-layer PCB. And even better on a 8 layer PCB where we can use striplines and multiple power planes.

(Shot no.2)

You're right about the 2.5V for Cyclone III (Altera messed that up ...). This is a (slight?) complication.

Maybe the ADC can run on 2.5V VccIO. Or else stick with Cyclone II.

A standard 4-layer board has a separation of about 700µ, so we could use use a 0.8 mm thick 2 layer PCB? Anyway the 100nF, 1nF capacitors on each VccInt ot VccIO pin will make up for the 'missing' plane capacitance.

an ep3c40f324 design i had done has passed all approvals without shielding on a 4 layer pcb with external signals of 96MHz so 4 layer is easy and can handle the additional 2,5v

you are slightly right and wrong. you can't just pick some values yu've got to place on your board. those values should be calculated depending upon the frequency response of your pcb. in fact the pcb itself is some kind of capacitor and inductor (and resistor) and has a resonace frequency at wich it turns from capacitive into inductive. so your first capacitor must have its pole theire, the next when the first turns into inductive and so on so the summ |Z| will be low enough. the |Z| depends upon the current you will need on that supply

if you just place some values you might get increased disturbance at certain resonance frequencies due to missaligned resonance behavioral of your components

thanks for all replies!

The ADC runs on 3.3V supply but I will need also the additional 1.2V and 2.5V (and maybe 1.8V) for the FPGA.... I'm planning to use only linears for that (no switching power supplies), eventually in parallel, to avoid additional noise.

The ADC accepts sinusoidal clock but we have strong requirements on jitter and thus I'll probably need to use a square-wave clock for the ADC, which in any case outputs a square clock for the FPGA...

I will probably end up with a 4-layer board, altough honestly I've never done boards with more than 2 layers so I'll need to study what's the best way to use the additional layers.

However I found only few docs about this topic:

- Altera's AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology

- Altera's Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines

- Avoiding PCB Design Mistakes in FPGA-Based Systems [http://www.altera.com/literature/wp/wp-01106-pcb-design-mistakes.pdf]

I probably will copy something from boards of evaluation modules :)

Unfortunately all PCB-related files coming with those evaluation boards are based on Cadence OrCAD tools for which I don't have a license (I'm going to use Cadsoft EAGLE to design the boards)... do you know perhaps a way to open those files without buying the licenses?

Thanks!

when you take some time to read all those app notes, be carefull. you should start to understand the basics of high speed designs and emc correct layouts. what are coupling mechanism, crosstalk, impedance controlled power supply why and how, how to correctly seperated analog from digital power supply, how to cross over slit planes, how to connect different GNDs together (Analog GND and Digital GND), return currents ...

the best adc is worth nothing when the layout itself disturbs everything

but the principals or the basic rules are easy, once you understood them you know where to look for.

if you want to open such files, ask for a demo version or a viewer only. or for a gerber viewing tool, most examples deliver the gerber files too