Assembling an FPGA board on 2 layers PCB

thanks for all replies!

The ADC runs on 3.3V supply but I will need also the additional 1.2V and 2.5V (and maybe 1.8V) for the FPGA.... I'm planning to use only linears for that (no switching power supplies), eventually in parallel, to avoid additional noise.

The ADC accepts sinusoidal clock but we have strong requirements on jitter and thus I'll probably need to use a square-wave clock for the ADC, which in any case outputs a square clock for the FPGA...

I will probably end up with a 4-layer board, altough honestly I've never done boards with more than 2 layers so I'll need to study what's the best way to use the additional layers.

However I found only few docs about this topic:

- Altera's AN 574: Printed Circuit Board (PCB) Power Delivery Network (PDN) Design Methodology

- Altera's Cyclone III Simultaneous Switching Noise (SSN) Design Guidelines

- Avoiding PCB Design Mistakes in FPGA-Based Systems [http://www.altera.com/literature/wp/wp-01106-pcb-design-mistakes.pdf]

I probably will copy something from boards of evaluation modules :)

Unfortunately all PCB-related files coming with those evaluation boards are based on Cadence OrCAD tools for which I don't have a license (I'm going to use Cadsoft EAGLE to design the boards)... do you know perhaps a way to open those files without buying the licenses?

Thanks!