Assembling an FPGA board on 2 layers PCB

(Shot no. 1)

Thinking a bit further on it.

I guess there are about 18 signals between the FPGA and the ADC and I guess about the same amount between the FPGA and the USB device, so we can connect each device to one side of the FPGA, leaving 2 sides totally free. (adding the configuration device and possibly a JTAG port may/will complicate things a bit)

The bottom side covered with gnd, except for a square under the FPGA which carries VccInt.

On the top layer we have a square (or 2 rectangles) under the FPGA to carry VccIO(s). All the signals are routed on the top layer, possible with gnd traces between them (at least for the clocks).

Using series termination to terminate the signal connections. (Unless we can keep the connections under 15mm)

The power supplies are routed in copper pour on the top layer as well.

Sprinkle a lot of capacitors (10µF, 100nF, 1nF) to decouple the power supplies.

Handling higher frequencies has to do with properly designing the transmission lines, not with the number of layers used. Also it is not really frequency that matters but the rise time of the signals. E.g, a 100 MHz clock and a 1HZ clock produce by a StratixII FPGA both have a rise time of 800 ps or so ...

But I totally agree it will be a lot quicker to design it / lay it out on a 4-layer PCB. And even better on a 8 layer PCB where we can use striplines and multiple power planes.