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Altera_Forum
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13 years ago

ask help for vhdl code of 1 bit memory

Hi, I am trying to write the code of 1bit SRAM, it has just read /write status. Give two signals we (write) and select_en (this memory cell is choose to work), then the date would be wrote in the memory and stored in Q,and date_out =data_in , otherwise is always in read status ,that means date_out always shows the date which is stored in Q. I was told the 1 bit memory was built by RS-Flip flop, but I don’t know how to combine it . Here is the code, if anyone can help me to check it,if I am totally wrong?

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

USE ieee.STD_LOGIC_unsigned.all;

entity SRAM_CELL is

port(

CLK : in std_logic;

date_in : in std_logic;

we : in std_logic;

select_en : in std_logic;

date_out : out std_logic

);

end SRAM_CELL ;

architecture BEHAVIORAL_SRAM_CELL of SRAM_CELL is

signal Q_state : std_logic;

attribute keep: boolean ;

attribute keep of Q_state : signal is true;

begin

process (clk,we)

begin

if CLK'event and CLK='1' then

if select_en CLK='1' then

if we='1' then

Q_state <= date_in;

end if;

end if;

end if;

end process ;

date_out <= Q_state ;

end BEHAVIORAL_SRAM_CELL;

Thank you

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    check the line »if select_en CLK='1' then«, I think you meant »if select_en='1' then«.

    Furthermore, the process doesn’t require we on the sensitivity list, so »process (clk)« is sufficient.

    Single VHDL signals, written in a clocked way like your Q_state, are implemented as registers, not memory. If you describe enough registers in the same entity in a way that the tool can recognize it as a one-dimensional n-bit memory-like array, it will automatically place a memory block in place. There are multiple issues with that: You have to keep some coding style such that the tool can correctly infer a memory block, and you might have to tweak code and attributes to guide the tool to infer the ‘right’ memory blocks in the ‘right’ configuration. Certainly, you are also free to directly instantiate a memory block straight from the Altera library, so you define what you want in a more structural manner. Check here (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf), page 11–13 to see how to write VHDL code that can be recognized as Altera FPGA memory.

    --- Quote Start ---

    I was told the 1 bit memory was built by RS-Flip flop, but I don’t know how to combine it .

    --- Quote End ---

    What do you want to achieve? Build RAM up from a collection of hand-crafted memory cells?

    – Matthias
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Matthias ,thanks for the info. I would like to build a 8 bit SRAM up from collection of memory cells and a Demultiplexer. I already wrote the memory cell code which I post upstairs and a Demultiplexer , I need combine them together. But I not sure how to do it. My thought is :

    since we have 5 input (clk,date_in (8 bit),address (8 bit),enable,write(we)) and one output date_out , through the Demultiplexer to decide which memory cell would be read and wrote.

    and now my problem is I don’t know how many memory cell do I need , is 8? And how combine them together also with Demultiplexer. Could you give me some advice?
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    So you want a 256x8 bit memory. Do you want to do this complex approach with separate demux and mux, single-cell memory entities etc. just for educational purposes, or do you want to achieve a real state-of-the-art FPGA block ram or distributed ram inferral?

    – Matthias
  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    Hi Matthias,

    I am sorry to reply so late. and like you said,what I have to do is write a VHDL code of 256*8 bit memory. Ijust started learning VHDL. This is a homework. The tipps I got is first write 1 bit register (RS-Flip Flop) and a demux.and then build them together a 256*8 bit memory.

    actually I don't understand the tipps.what i want to do is first write a group registers which can stored 8 bit date,that means I change the date_in.date_out,Q_state from std_logic to std_logic_vector in VHDLcodes upstairs. Is that right?

    and second about the Demux. I am not sure what's the function it is.is that :

    input a signal Enable and there are 256 output,decide which register vectore to be

    activated?

    and how can I make them together?