Honored Contributor
Honored Contributorcheck the line »if select_en CLK='1' then«, I think you meant »if select_en='1' then«.
Furthermore, the process doesn’t require we on the sensitivity list, so »process (clk)« is sufficient. Single VHDL signals, written in a clocked way like your Q_state, are implemented as registers, not memory. If you describe enough registers in the same entity in a way that the tool can recognize it as a one-dimensional n-bit memory-like array, it will automatically place a memory block in place. There are multiple issues with that: You have to keep some coding style such that the tool can correctly infer a memory block, and you might have to tweak code and attributes to guide the tool to infer the ‘right’ memory blocks in the ‘right’ configuration. Certainly, you are also free to directly instantiate a memory block straight from the Altera library, so you define what you want in a more structural manner. Check here (http://www.altera.com/literature/hb/qts/qts_qii51007.pdf), page 11–13 to see how to write VHDL code that can be recognized as Altera FPGA memory. --- Quote Start --- I was told the 1 bit memory was built by RS-Flip flop, but I don’t know how to combine it . --- Quote End --- What do you want to achieve? Build RAM up from a collection of hand-crafted memory cells? – Matthias
