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Honored Contributor
Honored Contributorask help for vhdl code of 1 bit memory
Hi, I am trying to write the code of 1bit SRAM, it has just read /write status. Give two signals we (write) and select_en (this memory cell is choose to work), then the date would be wrote in the mem...
Altera_ForumHonored Contributor
Honored ContributorHi Matthias ,thanks for the info. I would like to build a 8 bit SRAM up from collection of memory cells and a Demultiplexer. I already wrote the memory cell code which I post upstairs and a Demultiplexer , I need combine them together. But I not sure how to do it. My thought is :
since we have 5 input (clk,date_in (8 bit),address (8 bit),enable,write(we)) and one output date_out , through the Demultiplexer to decide which memory cell would be read and wrote. and now my problem is I don’t know how many memory cell do I need , is 8? And how combine them together also with Demultiplexer. Could you give me some advice?
