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Altera_Forum
Honored Contributor
14 years agoOne possible reason is that AS interface is more susceptible to signal integrity problems than JTAG. If you have a JTAG interface too, you should try to access the EPCS device through indirect JTAG programming (after generating a JIC file).
It would be interesting to know, at which memory location the verify fails, and if it's always the same. Another question is, if the configuration is accepted by the FPGA. It won't, if a CRC error is detected.