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KBloo3's avatar
KBloo3
Icon for New Contributor rankNew Contributor
4 years ago

AS & JTAG configuration issue on custom made CycloneIV EP4CE6F17C7N board

Hi all,

I hade this issue up in the Intel support earlier this summer, but I had some weeks of holiday and when I got back the thread was closed and I was directed to this place.

Could someone please give me some straight and honest answers of my questions?

Please don't ask me if I had followed the configuration guidelines.

Please read the thread below.

Best regards/Kenneth

Hi Aiman,

sorry for my late answer, I have had some weeks of holiday.

Yes, we have followed the configuration guidelines exept the pull-up on the nSTATUS signal.

Could you please comment my previous question about the nSTATUS signal?

"Is this nSTATUS signal just a signal that you can monitor or must it indeed be pulled up?"

I know the spec. says nSTATUS is a open drain, so to get it to toggle from logic '1' to logic '0'

or vice versa it has to be pulled-up, but do you really need it to be pulled-up?

Is not the need of pull-up only if you wan't to monitor the nSTATUS signal externally to see

when/if the chip is leaving the Reset MODE?

Could you please comment my previous question about the test I did?

"I have another type of circuit board, (a Cyclone IV E and the same SPI Flash), and I moved away the nSTATUS pull up resistor on that board. Still it is no problem to configure the FPGA from the SPI Flash, so I am little bit confused about the need of nSTATUS pull up resistor or not."

Should not this test prove that the pull-up resistor is recommended (so you can externally monitor it), but it is NOT mandatory.

A third and last question I have is:

Do one need to connect power to all I/O banks (1-8) even if you don't use some of the banks?

In our case we have left the VCC of I/O Bank 3 unconnected because we do not use I/O Bank 3 at all.

Let me be clear that we have VCC I/O Bank 1 & VCC I/O Bank 6 connected to power, because these two banks

are needed to configure the FPGA through AS or JTAG, but none of this configuration schemes are working.

Could the full reason of this issue depend on the fact that the VCC of I/O Bank 3 is NOT connected and therefore

the FPGA never leaves the Reset MODE?

Best regards,

Kenneth

6 Replies

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hello Kenneth,

    I will takeover Aiman's case to answer you.

    regarding nSTATUS pullup, from Cyclone IV schematic review worksheet,

    link: https://www.intel.com/content/dam/altera-www/global/en_US/others/download/board-layout-test/schematic-review-ws/worksheets/cyclone_10_lp_schematic_review_worksheet.doc

    nSTATUS is required to pullup to VCC via 10kOhm resistor(external). This is to make sure the nSTATUS turns logic HIGH when configuration completed and to make sure its stable.

    regarding VCCIO, same document, VCCIO[1..8] need to be powered up. This is the requirements to make sure the device functions as expected.

    regards,

    Farabi

    • KBloo3's avatar
      KBloo3
      Icon for New Contributor rankNew Contributor
      4 years ago

      Hi Farabi,

      no, at the moment there is no scopeshot for this design. We have only 2 boards and

      both of them was send away for X-ray, with the result that the FPGA:s soldering

      seemed to be ok.

      We have done an PCB update of this new design trying to make the design by the book.

      We are already far away in scedule of this project and very eager to final get this board to work.

      I/O Bank3 was left unconnected, because we did not use that bank at all, but now it is connected as well.

      Could you confirm that due to the fact that VCCIO pins of I/O Bank3 was left floating is the main reason

      to why the FPGA configuration mode never exit the Reset mode?

      The nSTATUS signal had NO pulled-up but it has now.

      I have asked this question on the forum several times before, but still don’t have get any answer:

      "I have another type of circuit board, (a Cyclone IV E and the same SPI Flash), and I moved away the

      nSTATUS pull up resistor on that board. Still it is no problem to configure the FPGA from the SPI Flash,

      so I am little bit confused about the need of nSTATUS pull up resistor or not."

      Should not this test prove that the pull-up resistor is recommended (so you can externally monitor it), but it is NOT mandatory?

      Best regards

      Kenneth

  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hello, Kenneth,


    nSTATUS need pullup as a requirement and its mandatory. Yes, you may see other setup dont have nSTATUS pullup and still working, but that can't be used for other setup. This setup has been tested in our lab and need to follow. I will have difficulty debugging if the circuit dont follow requirements as published in documentation.


    regards,

    Farabi


  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hello Kenneth ,


    All VCCIO need to power up as this is monitored by POR(Power On Circuitry), if one of the VCCIO not powered, POR will stuck the device in reset mode and not complete configuration.


    regards,

    Farabi


  • Farabi's avatar
    Farabi
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hello,


    I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.


    regards,

    Farabi