AS & JTAG configuration issue on custom made CycloneIV EP4CE6F17C7N board

Hi Farabi,

no, at the moment there is no scopeshot for this design. We have only 2 boards and

both of them was send away for X-ray, with the result that the FPGA:s soldering

seemed to be ok.

We have done an PCB update of this new design trying to make the design by the book.

We are already far away in scedule of this project and very eager to final get this board to work.

I/O Bank3 was left unconnected, because we did not use that bank at all, but now it is connected as well.

Could you confirm that due to the fact that VCCIO pins of I/O Bank3 was left floating is the main reason

to why the FPGA configuration mode never exit the Reset mode?

The nSTATUS signal had NO pulled-up but it has now.

I have asked this question on the forum several times before, but still don’t have get any answer:

"I have another type of circuit board, (a Cyclone IV E and the same SPI Flash), and I moved away the

nSTATUS pull up resistor on that board. Still it is no problem to configure the FPGA from the SPI Flash,

so I am little bit confused about the need of nSTATUS pull up resistor or not."

Should not this test prove that the pull-up resistor is recommended (so you can externally monitor it), but it is NOT mandatory?

Best regards

Kenneth