arriaII GX EPCS write by flash programmer

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arriaII GX EPCS write (sof,eld) by flash programmer

I succeeded to write hardware and software in EPCS using flash programmer in Cyclone III.

But I failed to write hardware and software in EPCS using flash programmer in Arria II GX.

I attach the process of cyclone III and arria II GX.

EPCS interface (DCLK,ASDO,nCSO,DATA0)can't be set as regular IO in Arria II GX, so can't sof nad elf file be written in EPCS by

flash programmer?

Other ways were mentioned at the end of attachment.

The way is to use flash memory and sram connected to regular IO.

Is this general?

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I am planning to set Active Serial configuration device (EPCS).Now I have not arria II GX board with EPCS.before programming,compile error occured. Arria II GX's DCLK ,DATA0,ASDO,nCSo are not dual purpose pins.So I cannot change them dedicate pins to regular IO pins.

But I used them as regular IO(IO port assign in RTL,pin assign in qsf ) .And I used EPCS flash controller IP in QSYS(for use flash programmer ).Is it possible by cyclone and then impossible by Arria II GX?I attach several system .Please tell something possible and something impossible to me in attachment.

I think you may not be able to do what you're trying to do with Arria II GX, for the reasons you've stated.

You can use the EPCS pins as regular I/O for Cyclone III (& Cyclone IV & V too). So, once the FPGA configuration image has loaded you can go on to use the same FLASH memory from which to boot Nios.

However, as you've stated, you can't assign DCLK, etc. as general purpose I/O when using Arria II GX. So, the EPCS is of no use once configuration of the FPGA has completed.

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The way is to use flash memory and sram connected to regular IO.

Is this general?

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You can connect FLASH memory and SRAM to general purpose user I/O, and the FLASH could be an EPCS. However, it will probably** have to be a separate device to the one used for configuring the FPGA - which is a shame.

** I say 'probably' - you could consider using external gates to allow access to the EPCS from both the FPGA's AS configuration pins and some general purpose I/O. A little more complicated than adding a second EPCS and may compromise the programming of the FPGA from it. However, I'm sure if it was thought through carefully it could be possible.

Cheers,

Alex

In you instanciate the 'JTAG to EPCS/Q bridge' (not sure what it is actually called) you then get an option to expose the epcs/q pins.

You can then attach your own bit-bang logic.

Thank you,

Again, I considered epcs_flash_controller .

I think,there is a difference in how to use epcs_flash_controller by cyclone III and arria II GX.

cyclone III use regular IO,but arria II GX use dedicate interface.

I confirmed that no compile error occured by setting dedicate AS interface in arria II GX.

BUt I don't have epcs device in arria II GX eva board(altera),so I can't confirm whether EPCS can be programed by a flash programmer.

I wrote mechanism(This is guess) of arriaIIGX on the last page of attachment.

If If it's wrong, please give me an advice.

Thank you,

Again, I considered epcs_flash_controller .

I think,there is a difference in how to use epcs_flash_controller by cyclone III and arria II GX.

cyclone III use regular IO,but arria II GX use dedicate interface.

I confirmed that no compile error occured by setting dedicate AS interface in arria II GX.

BUt I don't have epcs device in arria II GX eva board(altera),so I can't confirm whether EPCS can be programed by a flash programmer.

I wrote mechanism(This is guess) of arriaIIGX on the last page of attachment.

If If it's wrong, please give me an advice.