Honored Contributor
Honored ContributorI think you may not be able to do what you're trying to do with Arria II GX, for the reasons you've stated.
You can use the EPCS pins as regular I/O for Cyclone III (& Cyclone IV & V too). So, once the FPGA configuration image has loaded you can go on to use the same FLASH memory from which to boot Nios. However, as you've stated, you can't assign DCLK, etc. as general purpose I/O when using Arria II GX. So, the EPCS is of no use once configuration of the FPGA has completed. --- Quote Start --- The way is to use flash memory and sram connected to regular IO. Is this general? --- Quote End --- You can connect FLASH memory and SRAM to general purpose user I/O, and the FLASH could be an EPCS. However, it will probably** have to be a separate device to the one used for configuring the FPGA - which is a shame. ** I say 'probably' - you could consider using external gates to allow access to the EPCS from both the FPGA's AS configuration pins and some general purpose I/O. A little more complicated than adding a second EPCS and may compromise the programming of the FPGA from it. However, I'm sure if it was thought through carefully it could be possible. Cheers, Alex
