Arria10GX PCIE to RSU implementation

Hi,

For Intel Arria 10 devices, use Partial Reconfiguration over Protocol instead of CvP Update. You can use the PCIe bus to perform Partial Reconfiguration.

In CvP, you partition your design into two images: core image and periphery image.

• Periphery image (*.periph.jic) — contains general purpose I/Os (GPIOs), I/O registers, the GCLK, QCLK, and RCLK clock networks, and logic that is implemented in hard IP such as the JTAG interface, PR block, CRC block, Oscillator block, Impedance control block, Chip ID, ASMI block, Remote update block, Temperature sensor, and Hard IP for PCI Express IP Core. These components are included in the periphery image because they are controlled by I/O periphery register bits. The entire periphery image is static and cannot be reconfigured.

• Core image (*.core.rbf) — contains logic that is programmed by configuration RAM (CRAM). This image includes LABs, DSP, and embedded memory. The single static core image may include PR reconfigurable regions.
  
  • Reconfigurable region — This region can be programmed in user mode while the PCIe link is up and fully enumerated. It must contain only resources that are controlled by CRAM such as LABs, embedded RAM blocks, and DSP blocks in the FPGA core image. It cannot contain any periphery components such as GPIOs, transceivers, PLL, I/O blocks, the Hard IP for PCI Express IP Core, or other components included in the periphery image.
  • Static region — This region cannot be modified.

If you refer to the PCIe timing sequence in CvP mode, you will see that PCIe link is inactive during Periphery image configuration. PCIe link training happens after the Periphery image configuration is completed. Therefore, you can use the PCIe link to perform Core image configuration only. For Periphery image configuration, you have to use the conventional method such as JTAG.

intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_a10_cvp_prop.pdf

Thanks

Best regards,

KhaiY