GBeck
New Contributor
5 years agoArria10 IOPLL odd phase shift behavior
Seeing some strange behavior when performing a simulation of an IOPLL. The IOPLL is configured within a QSYS sub-system. The IOPLL utilizes a 125MHz ref clock. Multiple output clocks are required.
40MHz 0 degree phase shift, 45 degrees phase shift, 90 degree phase shift and 135 degree phase shift
We've been able to produce the necessary clocks using the attached file (system_altera_iopll_181_ves6lbi.vo.txt). Clock outputs 1-4 are used by the logic that requires the (4) 40Mhz clock with 45 degree phase difference. Clock outputs set to 0 and 180 degree phase shift do not produce expected results.
Not sure if these results are real or a simulation library issue. Has anyone experienced this before?
Regards, Gary