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GBeck's avatar
GBeck
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5 years ago

Arria10 IOPLL odd phase shift behavior

Seeing some strange behavior when performing a simulation of an IOPLL. The IOPLL is configured within a QSYS sub-system. The IOPLL utilizes a 125MHz ref clock. Multiple output clocks are required.

40MHz 0 degree phase shift, 45 degrees phase shift, 90 degree phase shift and 135 degree phase shift

We've been able to produce the necessary clocks using the attached file (system_altera_iopll_181_ves6lbi.vo.txt). Clock outputs 1-4 are used by the logic that requires the (4) 40Mhz clock with 45 degree phase difference. Clock outputs set to 0 and 180 degree phase shift do not produce expected results.

Not sure if these results are real or a simulation library issue. Has anyone experienced this before?

Regards, Gary

13 Replies

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor

    Thanks Gary for your inquiry. Allow me some times to take a look on your design before getting back to you.

    Eng Wei

  • EngWei_O_Intel's avatar
    EngWei_O_Intel
    Icon for Frequent Contributor rankFrequent Contributor

    Hi Gary

    From your attachment, we are seeing the setting as below:

    .phase_shift0("3125 ps"),
    .phase_shift1("3125 ps"),
    .phase_shift2("6250 ps"),
    .phase_shift3("9375 ps"),
    .phase_shift4("21500 ps"),
    .phase_shift5("0 ps"),
    .phase_shift6("0 ps"),
    .phase_shift7("0 ps"),
    .phase_shift8("0 ps"),

    which are 45degree shifted for outclock2,3,4, which are showing up in the waveform you have attached. Can you further describe the issue you are seeing?

    Thanks.

    Eng Wei

    • GBeck's avatar
      GBeck
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      If phase_shift0 is changed to 0 ps there a phase shift present

      Also if phase_shift0 is changed to 12500 ps the resulting shift is not 180 degrees.

      .phase_shift0("3125 ps"),
      .phase_shift1("3125 ps"),
      .phase_shift2("6250 ps"),
      .phase_shift3("9375 ps"),
      .phase_shift4("21500 ps"), // 309.6 degrees
      .phase_shift5("0 ps"),
      .phase_shift6("0 ps"),
      .phase_shift7("0 ps"),
      .phase_shift8("0 ps"),

      • GBeck's avatar
        GBeck
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        Adding modelsim capture with the following PLL settings

        .phase_shift0("0 ps"),
        .phase_shift1("3125 ps"),
        .phase_shift2("6250 ps"),
        .phase_shift3("9375 ps"),
        .phase_shift4("12500 ps"),
        .phase_shift5("0 ps"),
        .phase_shift6("0 ps"),
        .phase_shift7("0 ps"),
        .phase_shift8("0 ps"),

        Notice outclk_0 and outclk_4 phase shift is not as expected