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GBeck's avatar
GBeck
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5 years ago

Arria10 IOPLL odd phase shift behavior

Seeing some strange behavior when performing a simulation of an IOPLL. The IOPLL is configured within a QSYS sub-system. The IOPLL utilizes a 125MHz ref clock. Multiple output clocks are required....
EngWei_O_Intel's avatar
EngWei_O_Intel
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5 years ago

Hi Gary

From your attachment, we are seeing the setting as below:

.phase_shift0("3125 ps"),
.phase_shift1("3125 ps"),
.phase_shift2("6250 ps"),
.phase_shift3("9375 ps"),
.phase_shift4("21500 ps"),
.phase_shift5("0 ps"),
.phase_shift6("0 ps"),
.phase_shift7("0 ps"),
.phase_shift8("0 ps"),

which are 45degree shifted for outclock2,3,4, which are showing up in the waveform you have attached. Can you further describe the issue you are seeing?

Thanks.

Eng Wei

  • GBeck's avatar
    GBeck
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    5 years ago

    If phase_shift0 is changed to 0 ps there a phase shift present

    Also if phase_shift0 is changed to 12500 ps the resulting shift is not 180 degrees.

    .phase_shift0("3125 ps"),
    .phase_shift1("3125 ps"),
    .phase_shift2("6250 ps"),
    .phase_shift3("9375 ps"),
    .phase_shift4("21500 ps"), // 309.6 degrees
    .phase_shift5("0 ps"),
    .phase_shift6("0 ps"),
    .phase_shift7("0 ps"),
    .phase_shift8("0 ps"),

    • GBeck's avatar
      GBeck
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      5 years ago

      Adding modelsim capture with the following PLL settings

      .phase_shift0("0 ps"),
      .phase_shift1("3125 ps"),
      .phase_shift2("6250 ps"),
      .phase_shift3("9375 ps"),
      .phase_shift4("12500 ps"),
      .phase_shift5("0 ps"),
      .phase_shift6("0 ps"),
      .phase_shift7("0 ps"),
      .phase_shift8("0 ps"),

      Notice outclk_0 and outclk_4 phase shift is not as expected

      • GBeck's avatar
        GBeck
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        5 years ago

        Eng Wei,

        Curious if there have been any developments... Have you been able to re-produce the issue?

        Let me know if you have any questions.

        Thanks, Gary