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GBeck's avatar
GBeck
Icon for New Contributor rankNew Contributor
6 years ago

Arria10 IOPLL odd phase shift behavior

Seeing some strange behavior when performing a simulation of an IOPLL. The IOPLL is configured within a QSYS sub-system. The IOPLL utilizes a 125MHz ref clock. Multiple output clocks are required....
EngWei_O_Intel's avatar
EngWei_O_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Thanks Gary for your inquiry. Allow me some times to take a look on your design before getting back to you.

Eng Wei