malayali
New Contributor
3 years agoArria10 FPGA SERDES details
hello Team,
I am using Arria 10 FPGA my design. My application is USB (Host and device) and DP (Source and sink). I am using the Transceiver bank for the USB and DP interface and I have a few queries in it.
1. When FPGA is in DP Sink or USB Device [Receiver] mode will there be any common-mode voltage or bias voltage to the Multiplexer IC from [TMUXHS4412] since am MUX the USB and DP Signals via these mux to the USB - C Connector.
2. What is the common-mode voltage of the transceiver bank in Source and Sink USB or DP IP?