Arria V SoC HPS EMAC 1588 PTP Feature

I have a similar issue.

On my DE10-Nano design, I am using the Ethernet as connected under Linux, and it works fine: DHCP, ssh, etc. I want to leave the Ethernet as it is, except that I simply want to access the three EMAC to FPGA IEEE1588 Timestamp Interface signals defined in the HPS technical reference manual. If in my VHDL module, I define

component cyclone_hps_interface_peripheral_emac

generic (lpm_type : string := "cyclone_hps_interface_peripheral_emac");

port(

ptp_aux_ts_trig_i : in std_logic;

ptp_pps_o : out std_logic;

f2h_emac_ptp_ref_clk : in std_logic

);

and

emacI0: cyclone_hps_interface_peripheral_emac

port map(

ptp_aux_ts_trig_i => ptp_aux_ts_trig_i,

ptp_pps_o => ptpPps0hps

);

then, in the Quartus post-fit viewer, there is a box named "emacI0" with the input driven with my ptp_aux_ts_trig_i logic and the output appropriately routed. The resulting image still has a functional Ethernet. I assume that this means that the fitter could find the requested connectivity.

If I include f2h_emac_ptp_ref_clk as an input on the component, then connect it to a signal, the Quartus fitter complains that the new port doesn't exist in primitive cyclonev_hps_interface_peripheral_emac, which it indeed doesn't in quartus/libraries/vhdl/wysiwyg/cyclone_components.vhd, where cyclone_hps_interface_peripheral_emac is defined.

There is no signal f2h_emac_ptp_ref_clk in that file, but there is a port ptp_ref_clk on a component called cyclone_hps_interface_clocks_resets. However, when I try instantiating that component with a port of either f2h_emac_ptp_ref_clk or ptp_ref_clk, the fitter complains about duplicate instances of HPS_INTERFACE_CLOCKS_RESETS.

Qsys appears to provide no means by which the PTP reference clock can be edited into the Arria V/Cyclone V Hard Processor System. There is an "Enable EMAC0 Precision Time Protocol (PTP) FPGA Interface" check box in the "FPGA Interfaces" tab of the HPS, but it is grayed out.

How do I make a connection to f2h_emac_ptp_ref_clk? Can I edit that pin onto the HPS in Qsys? Maybe that would be possible if the check box weren't grayed out. How can I enable the check box to find out? Is there an edit I can make to a file in the quartus release directory or the Quartus-generated files in the compilation directory to make the signal visible? This is an essential feature I am depending on in my design, but I can't use it if the tools won't let me connect to it.

Thanks for your help.

By hand-editing soc_system.qsys t

<parameter name="EMAC0_PTP" value="true" />

the checkbox is grayed-out, but checked. If the Peripheral Pins->EMAC0 pin: is set to FPGA, hps_0.emac_ptp_ref_clock becomes visible. Unfortunately, so do hps_0.emac_rx_clk_in and hps_0.emac_tx_clk_in, and some others, too. It isn't clear just how to deal with these signals, which appear to be required by Qsys, even though they aren't physically required.

How do I deal with these signals to maintain the same Ethernet behavior as before, with a visible ptp_ref_clk?

If in Qsys I connect hps_0.emac_tx_clk_in and hps_0.emac_ptp_ref_clock up to the reference clock from my design, the design compiles and there is still a functional Ethernet, despite all of the new Ethernet signals which show up as a consequence of making the above changes, so there doesn't seem to be a need to deal specially with these signals. The problem now, however, is that Qsys reports my drive signal for hps_0.emac_ptp_ref_clock and hps_0.emac_tx_clk_in with the warning "Interface has no signals," even though they are clearly connected to my drive signal. The result in the post-fit netlist viewer has no string "ptp_ref_clock" in it, so I'm missing something in ensuring connectivity. Soc_system/synthesis/soc_system.vhd contains the line

emac_ptp_ref_clk => open,

so Qsys seems to refuse to make the connection I'm requesting.

How can I get Qsys to make the connection?