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JOter's avatar
JOter
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7 years ago

Arria V-Quartus 18/18.1 time quest constrains.

I have problems, with a Arria V-Quartus 18/18.1 and time quest constraints. It seems quartus does not apply the constraints file. The same Project Works properly with a cyclone III and Q13.1.

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  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    6 years ago

    Hi,

    I haven't the numeric results, we didn't anotate them. We tested it with wide range of data output delays (for example from 0 to 8ns)

    You must take into acount that the same project works properly with a cyclone III and Q13.1. So we are looking for a problema in our "Q18 and Arria V" Project, or in Q18 compiler.

    Best regards

  • KhaiChein_Y_Intel's avatar
    KhaiChein_Y_Intel
    Icon for Regular Contributor rankRegular Contributor
    6 years ago
    Hi, The value that you see in the Timing report is the worst case scenario. Is the output delay in the hardware exceed the value in the timing report? Thanks.
  • JOter's avatar
    JOter
    Icon for New Contributor rankNew Contributor
    6 years ago

    ​I'm sorry but I didn't see your message. At the end I didn't use any "output_delay", I only used the clock phase shift.

    I try to summarize the case. I used the next configuration:

    create_clock -name PSRAM_CLK -period 16 [get_ports {PSRAM_CLK}]

    create_generated_clock -name vt_PSRAM_CLK -source [get_ports {PSRAM_CLK}] -divide_by 1 -multiply_by 1 -phase 180

    set_output_delay -clock {vt_RAM_CLK} 2 [get_ports {RAM_A* }]

    Signal meaning:

    PSRAM_CLOCK: RAM mem. clk generated in a FPGA-PLL

    RAM_A: RAM mem, addr.I

    Both signals were monitoring with one oscilloscope. The delay between both was almost constant for any "set_output_delay" value, quite different to the programmed value.