Arria V-Quartus 18/18.1 time quest constrains.

​I'm sorry but I didn't see your message. At the end I didn't use any "output_delay", I only used the clock phase shift.

I try to summarize the case. I used the next configuration:

create_clock -name PSRAM_CLK -period 16 [get_ports {PSRAM_CLK}]

create_generated_clock -name vt_PSRAM_CLK -source [get_ports {PSRAM_CLK}] -divide_by 1 -multiply_by 1 -phase 180

set_output_delay -clock {vt_RAM_CLK} 2 [get_ports {RAM_A* }]

Signal meaning:

PSRAM_CLOCK: RAM mem. clk generated in a FPGA-PLL

RAM_A: RAM mem, addr.I

Both signals were monitoring with one oscilloscope. The delay between both was almost constant for any "set_output_delay" value, quite different to the programmed value.