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Altera_Forum
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13 years ago

Arria V B3 ES: Problems in FPLL and pin placement

Hello,

I get a can't fit design in device error while evaluating my pinning. I use a Arria V B3 Engineering Sample with 1152 pin package (5AGXFB3H6F35C6ES).

The whole upper side of the device (Bank 7 and 8) are used to get five source synchronous interfaces with DDR LVDS at 200MHz, edge-aligned. For each interface the strobe clock is generated by a separate RX PLL that shifts the clock by about 90 degree (source synchronous mode). Therefore I use the differential clock input pins of each PLL. Two on the left, two at the center and one on the right side (top view).

In addition there is a PLL (Normal Mode) that generates the main clocks used within the design. It should generate 50, 100, 150, 200 (TX clock for all LVDS interfaces), 240, and 300 MHz out of 50 MHz LVDS. Those clocks need to go on the GCLK. There is no possibility that I can use another clock input for the "main pll" since all other banks have an incompatible IO standard (1.5V for SSTL15).

When compiling this setup I get the Can't fit design in device error:

Error (175001): Could not place fractional PLL lvds_rx_pll:lvds_rx_pll_1|pll_lvds_rx_90deg:pll_cpu|pll_lvds_rx_90deg_0002:pll_lvds_rx_90deg_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL

Error (177014): Invalid port found on the path from fractional PLL feedback output lvds_rx_pll:lvds_rx_pll_1|pll_lvds_rx_90deg:pll_cpu|pll_lvds_rx_90deg_0002:pll_lvds_rx_90deg_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL to destination lvds_rx_pll:lvds_rx_pll_1|pll_lvds_rx_90deg:pll_cpu|pll_lvds_rx_90deg_0002:pll_lvds_rx_90deg_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL

Error (184041): fractional PLL lvds_rx_pll:lvds_rx_pll_1|pll_lvds_rx_90deg:pll_cpu|pll_lvds_rx_90deg_0002:pll_lvds_rx_90deg_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL could not be placed into any device location to satisfy its connectivity requirements

Error (184041): fractional PLL lvds_rx_pll:lvds_rx_pll_1|pll_lvds_rx_90deg:pll_cpu|pll_lvds_rx_90deg_0002:pll_lvds_rx_90deg_inst|altera_pll:altera_pll_i|general[0].gpll~FRACTIONAL_PLL could not be placed into any device location to satisfy its connectivity requirements

When I remove the Normal PLL in the upper right corner Quartus can use the LVDS receive clock pin like it should. If I throw the normal clock input back in, again I get the can't fit error. Changing the location of the LVDS receive clock pin does not solve that error. In the datasheet it says that two FPLLs share four single-ended or differential clock input pins. In my understanding I could use those two FPLLs together completely independantly except that they share the output counters.

Did I miss any restriction in PLL Clk Input placement? What can I do?

Thank you.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    13 years ago

    with such a new chip, I suggest raising a support request with altera mysupport, incase you dont get a response here.

  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    I'm struggling with what seems like a very similar issue (Arria V GZ). I've got a handful of TX/RX ALT_LVDS modules instantiated that use my "PIN" clock as the primary reference clock (tx|rx_inclock) and then they end up merging Tx/Rx PLLs, per the megawizard setting so that it appears that the 8x RX and 8x TX pairs all use one PLL. I also am using the PIN clock to derive a handful of other rates (2x, 1/2x, phase shift, etc) for my core logic in the design. I've found that if I keep this PLL in the design, I get an error messages stating that I can't place the LVDS PLLs. If I just use the PIN clock directly to drive the logic, everything works OK. I know that the Arria V devices have restrictions on the CLKn input ports and which PLLs can be driven by them, but I'm using 2 of the 4 available FRACPLLs for the 4 input ports, of which this PIN clock is one of them (CLK8-CLK11). So there should be one available.

    With all of that said, did you come up with a solution to your issue? I realize that it was about a year ago, but I still figured I'd ask. What has me vexed is that I removed the pin constraint for this PIN clock and then rebuilt, and it still failed. I would expect that if there was a pin that would work for it, it would use that one and then report it in the pin planner.

    One thing that I'm in the middle of trying is dropping in a CLKCTRL block around the fabric clock PLL to see if that makes a difference. I found an Altera answer record that had something to do with this block resolving this sort of issue. I tried putting one in front of the fabric PLL and it didn't make any difference. I'm currently building with the PIN clock driving the fabric PLL and then putting a CLKCTRL block before the ALTLVDS clock inputs. We'll see how that goes.

    Any input would be appreciated.

    Jeff
  • Altera_Forum's avatar
    Altera_Forum
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    12 years ago

    Hi,

    the clock routing restrictions in the Arria V GX project are based on errors in the ES-devices (-> Errate Sheet). It was not possible to drive GCLKs from this PLL and so quartus was not able to fit the design.

    The ALTLVDS_RX (and TX) megacores use dedicated clock networks to drive the I/O registers / SERDES Blocks. There is also a PLL instantiated inside ofthe RX part so this may be a reason if you are running out of PLLs. Also note that there are restrictions in the pinplacement of the I/O pins. Refer to pin placement guideline section in the arriav handbok (-> no interleaving allowed).

    Another this I would try is instantiating the PLL by my own and using the ALTLVDS_TX in "External PLL" mode.

    Regards