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Altera_Forum
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13 years ago

Arria V B3 ES: Problems in FPLL and pin placement

Hello, I get a can't fit design in device error while evaluating my pinning. I use a Arria V B3 Engineering Sample with 1152 pin package (5AGXFB3H6F35C6ES). The whole upper side of the d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

with such a new chip, I suggest raising a support request with altera mysupport, incase you dont get a response here.