Honored Contributor
Honored ContributorI'm struggling with what seems like a very similar issue (Arria V GZ). I've got a handful of TX/RX ALT_LVDS modules instantiated that use my "PIN" clock as the primary reference clock (tx|rx_inclock) and then they end up merging Tx/Rx PLLs, per the megawizard setting so that it appears that the 8x RX and 8x TX pairs all use one PLL. I also am using the PIN clock to derive a handful of other rates (2x, 1/2x, phase shift, etc) for my core logic in the design. I've found that if I keep this PLL in the design, I get an error messages stating that I can't place the LVDS PLLs. If I just use the PIN clock directly to drive the logic, everything works OK. I know that the Arria V devices have restrictions on the CLKn input ports and which PLLs can be driven by them, but I'm using 2 of the 4 available FRACPLLs for the 4 input ports, of which this PIN clock is one of them (CLK8-CLK11). So there should be one available.
With all of that said, did you come up with a solution to your issue? I realize that it was about a year ago, but I still figured I'd ask. What has me vexed is that I removed the pin constraint for this PIN clock and then rebuilt, and it still failed. I would expect that if there was a pin that would work for it, it would use that one and then report it in the pin planner. One thing that I'm in the middle of trying is dropping in a CLKCTRL block around the fabric clock PLL to see if that makes a difference. I found an Altera answer record that had something to do with this block resolving this sort of issue. I tried putting one in front of the fabric PLL and it didn't make any difference. I'm currently building with the PIN clock driving the fabric PLL and then putting a CLKCTRL block before the ALTLVDS clock inputs. We'll see how that goes. Any input would be appreciated. Jeff
