Honored Contributor
Honored ContributorHi,
the clock routing restrictions in the Arria V GX project are based on errors in the ES-devices (-> Errate Sheet). It was not possible to drive GCLKs from this PLL and so quartus was not able to fit the design. The ALTLVDS_RX (and TX) megacores use dedicated clock networks to drive the I/O registers / SERDES Blocks. There is also a PLL instantiated inside ofthe RX part so this may be a reason if you are running out of PLLs. Also note that there are restrictions in the pinplacement of the I/O pins. Refer to pin placement guideline section in the arriav handbok (-> no interleaving allowed). Another this I would try is instantiating the PLL by my own and using the ALTLVDS_TX in "External PLL" mode. Regards
