Arria V 64-Bit multiplication

I noticed while running Quartus timing analysis on a simple 64x64 bit multiplication (with 2 pipeline stages) on the Arria V board that I was getting very low Fmax values.

Looking into the Chip Planner a little, I also noticed that the circuit only packed 1 pipeline register into the DSP (the DSP input register set) and the output register set was left unused.

What I am confused by is that the "auto register packing" setting is set to "AUTO" and it is not working as I would like.

These settings work with 8-bit, 16-bit and 32-bit pipelined multiplication, but not for 64-bit. I have been reading a little on the architecture and it looks like the high precision DSP mode can operate at most in a 27x27 bit multiplication mode - does this have any relevance?

If not, any ideas why this might be the case?

Any advice is well appreciated!

Thanks in advance.