Arria II GX SerDes - lowest data rate

Thanks for the link, the pancake.

The problem is the documentation is inconsistent ... there are other locations which imply the part can run at OC-3 rates (155 Mbps). I also believe the minimum rate is 600 Mbps as you pointed out - an FAE indicated it is the lower limit of the CDR PLL - but there is an FPGA designer here who believes ha can recover a 125 Mbps stream in the SerDes as long as the FPGA also gets the clock (on separate pins) along with the data.

I'm looking to see if anyone else has experience doing this.