Arria 10 SoC EMIF Input clock jitter requirment

Hi Alpar,

Thank you for submitting your question in Intel Community.

I'm Adzim, application engineer will assist you in this thread.

"An input jitter of 10 ps peak-to-peak is mentioned @ Table 55. in the datasheet, but we do not know what type of jitter is it (period jitter/TIE/cycle-to-cycle jitter)."

I've checked with internal team and they stated that the TIE(phase) Jitter spec for clock oscillator is not more than 10ps PK or the equivalent RMS jitter is 1.42ps at 10e-12 BER or 1.22ps at 10e-16 BER.

The Arria 10 SoC Devkit has used Si5338 programmable oscillator which is has phase jitter of 0.7ps RMS typ and it's still within the spec.

I think the crystal oscillator that you used is still within the spec as well because the phase jitter is at 0.8ps RMS typ.

Regards,

Adzim