Forum Discussion
FabianL
Occasional Contributor
Occasional ContributorArria 10: Remote Update may brick FPGA and Factory Fallback won't work
Hello, we have observed some critical failures when doing tests with various potential error scenarios concerning a remote Update of the FPGA bitstream in the attached SPI Flash device. We could re...
lixy
Contributor
ContributorHi Fabian,
- First, can you ensure that in normal scenario, the factory/application images are configured successfully? Eg. It can load to factory/application images as expected when we set the RU_PAGE_SELECT same as the start address when generating the .jic file.
- Besides, our internal team have tested Remote update on A10 SX SoC dev kit via AVMM interface, where we set some of the RU register as shown below. Maybe you can refer to our setting as reference or can we have the customer parameter setting for us to replicate it? https://www.intel.com/content/www/us/en/docs/programmable/683695/19-4-19-1-0/register-map-12579.html
|
Register Bame |
Address offset |
Write value |
|
RU_WATCHDOG_ENABLE |
0x2 |
1 |
|
RU_WATCHDOG_TIMEOUT |
0x1 |
F |
|
RU_PAGE_SELECT |
0x3 |
01E28000 (refer to the start address when they generate the .jic file) |
|
RU_CTL_NUPDT |
0x7 |
1 |
|
|
|
|
Best Regards,
Xiaoyan
