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Altera_Forum
Honored Contributor
Honored ContributorArria 10 reclk frequency limitations of fPLL
When instantiating an fPLL (in Qsys) with a reference clock frequency of 50 MHz the fitter reports the following error:
Error (15653): The Fitter cannot find a legal configuration for the follo...
Altera_ForumHonored Contributor
Honored ContributorThe desired output frequency is 24 MHz. Qsys seems to be ok with that ;)
