arria 10 lvds serdes

Hi @HortumNecmi @LLCC ,

I'm facing the same issue, but I already have the bits connected to an input port on one end and to an intermediate pin on the other end. I have this piece of code on my toplevel HDL and I'm not sure what is still missing.

-- group the block/polarization data together for the serdes IPs
    adc_if_0x_rx_in <= T1_X_FCLK & T1_R8X_I & T1_R8X_Q & 
                       T1_X_FCLK & T1_R7X_I & T1_R7X_Q & 
                       T1_X_FCLK & T1_R6X_I & T1_R6X_Q & 
                       T1_X_FCLK & T1_R5X_I & T1_R5X_Q & 
                       T1_X_FCLK & T1_R4X_I & T1_R4X_Q & 
                       T1_X_FCLK & T1_R3X_I & T1_R3X_Q & 
                       T1_X_FCLK & T1_R2X_I & T1_R2X_Q & 
                       T1_X_FCLK & T1_R1X_I & T1_R1X_Q;

-- some code in between

-- LVDS SERDES
    adc_if_0x : component lvds_tile
    port map (
        inclock             => FPGA_REFCLK_ADC, -- adc_sample_clk 50 MHz
        pll_areset          => core_reset,
        pll_locked          => adc_if_0x_pll_locked,
        rx_in               => adc_if_0x_rx_in,
        rx_out              => adc_if_0x_data_out,
        rx_coreclock        => adc_if_0x_rx_coreclock, -- 50 MHz (SERDES Factor 7)
        rx_dpa_reset        => adc_if_0x_rx_dpa_reset,
        rx_dpa_locked       => adc_if_0x_rx_dpa_locked,
        rx_bitslip_ctrl     => adc_if_0x_rx_bitslip_ctrl,
        rx_bitslip_reset    => adc_if_0x_rx_bitslip_rst
    );

The lvds_tile component was defined and added to the project. I'm not getting any syntax error. I'm using a 24 channel approach (see the concatenation at line 2) with a serialization factor of 7. But I'm getting errors like the error given below (I get it for all 24 bits of channel[]) when I try to compile on Quartus Pro 21.3. I've verified that the Platform Designer connects 'adc_if_0x_data_out' to an intermediate block as well, so it's not optimized away either.

I'd be appreciated if you could give me a hand here.

Cheers

Error(129015): Output port RXDATA on atom "adc_if_0x|lvds_tile|core|arch_inst|channels[23].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a cyclone10gx_io_serdes_dpa primitive, is not legally connected and/or configured
Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected
Info(129016): Output port RXDATA[6] is disconnected, but the Compiler expects this output port to be connected
Info(11951): Module instance "adc_if_0x|lvds_tile|core|arch_inst|channels[0].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 7 connected to TXDATA port.