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Re: arria 10 lvds serdes
Thank you. I have already solved this problem. My feeling is that when the data output by this IP is being processed logically, it requires data from all channels to be used together. For example, if I only use the output data from a single channel to complete a certain logical process, while the output data from other channels is used for another logical process, it may trigger the aforementioned error.1.5KViews0likes0Commentsarria 10 lvds serdes
hello, I was originally using the quartus 17.1 Standard Edition to complete some designs that include LVDS SERDES IPs, and the projects were able to pass compilation successfully. However, when I migrated these projects to 22.1 Pro, compilation errors occurred, even though I am certain that the designs are identical to the original versions. Here are one of the details of the error messages encountered： Error(129015): Output port RXDATA on atom "data_rx_top_u0|one_rx_module_u3|lvds_rx_u0|chan17_u0|lvds_0|core|arch_inst|channels[9].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive, is not legally connected and/or configured Info(129016): Output port RXDATA[0] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[1] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[2] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[3] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[4] is disconnected, but the Compiler expects this output port to be connected Info(129016): Output port RXDATA[5] is disconnected, but the Compiler expects this output port to be connected Info(11951): Module instance "data_rx_top_u0|one_rx_module_u3|lvds_rx_u0|chan17_u0|lvds_0|core|arch_inst|channels[9].dpa_fifo.ioserdesdpa.serdes_dpa_inst", which is a twentynm_io_serdes_dpa primitive and belongs to an ALTLVDS interface, should have a bus width of exactly 6 connected to TXDATA port. "I am very sure that the code is correct, and it compiled and passed simulation successfully in the 17.1 Standard Edition. Why am I encountering compilation errors in 22.1 Pro?"1.8KViews0likes10Comments