Arria 10 Low Latency 40G Ethernet Fails to compile with VHDL

Hello Zi,

Thanks for taking a look at this. I agree with you that the REFCLK is not connected to the IO PLL. However, the IO PLL is instantiated and connected by the Platform Designer Generated HDL as part of the 40G MAC core. The only other external entity I am hooking up to the core is the ATX PLL for the transceiver TX Serial Clock. Below is a picture of the design I am trying to evaluate, it is essentially what is shown in Figure 7 of the Low Latency 40Gbps Ethernet IP User Guide (Doc #683745). And again I will emphasize, this error only occurs when I select VHDL as the Generated HDL output from platform designer. The Verilog Generated HDL does not have this problem. Attached is the .QAR file if you would like to open it and compile.

Thanks,

Chris