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civey0207's avatar
civey0207
Icon for New Contributor rankNew Contributor
2 years ago
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Arria 10 Low Latency 40G Ethernet Fails to compile with VHDL

Hello, I'm trying to evaluate the Low Latency 40G Ethernet core in a VHDL based design. The settings of the core are the same as the example design. I've instantiated the ATX PLL that comes with ...
  • ZiYing_Intel's avatar
    ZiYing_Intel
    2 years ago

    Hi civey0207,


    I think you see the error in synthesis stage might due to the IOPLL instance in Intel Arria 10 design is not connected to a valid REFCLK signal.


    Best regards,

    Zi Ying


ZiYing_Intel's avatar
ZiYing_Intel
Icon for Frequent Contributor rankFrequent Contributor
2 years ago

Hi civey0207,


Can share your .qar file here? So that I can try debug the issue from my side.


Best regards,

Zi Ying