Arria 10 GX configuation time vs. PCIe requirement

I've been charged with figuring out a configuration scheme for our Arria 10 design that will incorporate a PCIe interface. I've attached an image of what I've come up with

There is a 100ms configuration requirement if you are using PCIe. So to get my device to configure (270K GX part 10AX027H3F35), I have learned that basically we'll have to do a x32 configuration scheme running at 100MHz between our configuration host (MAXV with parallel flash loader) and the FPGA. This should load our FPGA in 38.4ms.

The problem I am having is that I have to use FLASH storage for the bit file, and I just can't see how we can pull data out of the FLASH fast enough to feed the HOST => FPGA interface. I'm doing a 32 bit interface to the flash as well, using two 16 bit FLASH parts, and the "Parallel Flash Loader IP Core User Guide" says that the flash_clk speed is half the core source clock (125MHz/2 =62.5Mhz). Doing rough math, even at the most optimal burst rate:

• 122,591,622 bits for Arria 10 10AX027H3F35.

• 32 bit interface from FLASH to HOST

• 32 bits from HOST to FPGA configuration interface

• 122,591,622/32 bits = 3830988 cycles @ 62.5MHZ (optimum BURST rate - not realistic full time) = 3830988*16nS = 61mS.

• The above 61ms < 100mS. Sounds fine, but read on.

What is confusing to me, I'm trying to use the Arria 10 Development kit as a baseline and sanity check. Their configuration time, considering the size of the FPGA would never make it for PCIe.

• 351,292,512 bits for Arria 10 10AX1157N2F35.

• 32 bit interface from FLASH to HOST

• 32 bits from HOST to FPGA configuration interface

• 351,292,512/32 bits = 10977891 cycles @ 25MHZ - yes their config HOST clk is 50Mhz (optimum BURST rate - not realistic full time) = 10977891*40nS = 439mS.

• The above 439ms >> 100mS. This makes PCIe use impossible.

questions:

1) So I think what I am missing is my calculation for my 65nS FLASH parts with a 32 bit interface. Am I right to assume that the raw bit files are being stored in FLASH? IS there some sort of compression on the store to FLASH, then decompression in the parallel programmer IP that expands a much smaller configuration file? the A10 Developer Kit User guide defines USER hardware1/2 as 44,032 KB in the Flash memory space. This jives with the 351,292,512 bit size defined in the Arria 10 device guide for programming file. So Im inclined to believe there's that many bits to move.

2) If you are using a Hard IP core for the PCIe does the 100mS configuration requirement go away? Dumb question, but is that only for soft PCIE?

Any help you can offer is greatly appreciated.