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Indumathi's avatar
Indumathi
Icon for New Contributor rankNew Contributor
5 years ago

Arria 10 FPGA Unpowered State

Hi Team, I am designing an Arria 10FPGA Board For USS 3.0 GEN2 10 G Interface. I am new to this FPGA Based Design as well as multiple processors in one board. Could you please guide me and answer t...
HBhat2's avatar
HBhat2
Icon for Contributor rankContributor
5 years ago

Hi Amin,

"The Arria® 10 device dedicated transceiver pins are not subject to the same hot-socketing limitations of the general purpose I/O pins. It is OK to drive the dedicated transceiver pins during power-up and power-down sequencing of Arria 10 devices."

Above statement is confusing with

"Fully configure the transceiver block before driving or having any activity on the Intel Cyclone 10 GX and Intel Arria 10 device transceiver pins." This statement is in the below link. "1.3.2. Transceiver Pin Guidance for Unpowered FPGA " page 14

https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/an/an692.pdf

Is it possible to correlate above statement with statement in an692?

With Regards,

HPB

AminT_Intel's avatar
AminT_Intel
Icon for Regular Contributor rankRegular Contributor
5 years ago

Hello,

Yes. The first statement described the process during power-up and power-down while the second statement described about configuring for unpowered FPGA.

Thanks.