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Honored Contributor
Honored ContributorArray make's logic or uses BRAM?
Hi I'm working on a project with a cyclone III ( EP3C10F256C8).
In the project en monitoring with a camera. I need to write a code who finds the position of the brightest pixel in the image. I made an array for the full lengt (1280 columns) of 8 bit. When I recieve the first line of the camera, i compare the value of the corresponding column with a value of a register who memory's the maximum value (brightest pixel). If it is a higher (brighter) value , then i place the number line (position) in a position_register. If the camera has sended the image is read out the position_register. The problem si that the compiler doesn't use BRAM and the logic generated for the process is to big for the device. How can i force it to use BRAM ? (Working in Quartus II v8.0) The code i wrote:
library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity VERTICAL_COUNTER is
generic
(
Write_adress : std_logic_vector (22 downto 0) := "000" & x"00000"
);
port
(
RESETn : in std_logic;
CLK100MHz : in std_logic;
CAM_DATA_VALID : in std_logic := '0';
CAM_DATA : in std_logic_vector (7 downto 0) ;
CAM_FRAME_VALID : in std_logic := '0';
CAM_LINE_VALID : in std_logic := '0';
COUNTER_ABLE : in std_logic := '0';
DATA_VALID : out std_logic := '0';
DATA_OUT : out std_logic_vector (7 downto 0) ;
FRAME_WRITE_ADR : out std_logic_vector (22 downto 0);
WRITE_ABLE : out std_logic := '0'
);
end entity;
architecture rtl of VERTICAL_COUNTER is
signal buff_CAM_LINE_VALID : std_logic_vector (1 downto 0) := (others => '0');
signal send_data : std_logic := '0';
signal line_counter : integer range 0 to 255 := 0;
signal column_counter : integer range 0 to 1279 := 0;
signal max_column : integer range 0 to 1279 := 0;
type array_type is array (0 to 1279) of unsigned (7 downto 0);
signal array_position , array_amplitude : array_type;
begin
FRAME_WRITE_ADR <= Write_adress;
prog_adr : process (CLK100MHz) begin
if rising_edge (CLK100MHz) then
buff_CAM_LINE_VALID <= buff_CAM_LINE_VALID(0) & CAM_LINE_VALID;
if CAM_FRAME_VALID = '1' and COUNTER_ABLE = '1' then
send_data <= '1';
if CAM_LINE_VALID = '1' then
if CAM_DATA_VALID = '1' then
column_counter <= column_counter +1 ;
if unsigned (CAM_DATA) >= array_amplitude(column_counter) then
array_position(column_counter) <= to_unsigned (line_counter, 8);
array_amplitude(column_counter) <= unsigned (CAM_DATA) ;
end if;
end if;
end if;
if buff_CAM_LINE_VALID = "10" then
line_counter <= line_counter + 1;
if column_counter > max_column then
max_column <= column_counter;
else
max_column <= max_column;
end if;
column_counter <= 0;
end if;
else -- cam frame valid = 0
if send_data = '1' then
DATA_VALID <= '0';
WRITE_ABLE <= '1';
if column_counter >= max_column then
send_data <= '0';
column_counter <= 0;
max_column <= 0;
else
DATA_VALID <= '1';
column_counter <= column_counter +1 ;
DATA_OUT <= std_logic_vector (array_position(column_counter));
end if;
else
WRITE_ABLE <= '0';
column_counter <= 0;
line_counter <= 0;
array_amplitude <= (OTHERS => (OTHERS => '0'));
array_position <= (OTHERS => (OTHERS => '0'));
end if;
end if;
end if;
end process;
end rtl;
