Forum Discussion
Altera_Forum
Honored Contributor
Honored Contributorarray initialization on separate file in verilog
hello...
can i initialize array in separate file n use it in another file.. like in file (define.v) a[0]=1; a[1]=2; want to use this definition in another file (main.v) module input in; output etc etc; reg [1:0] a[0:1]; `include "define.v" endmodule but its nt working... help!!!1 Reply
Altera_ForumYou can use the "`include" to accomplish what you are trying to accomplish. However, you need to read the following coding guidelines on how to initialize memory:
http://www.altera.com/literature/hb/qts/qts_qii51007.pdf Read the section "Specifying Initial Memory Contents at Power-Up" starting on page 6-27 Jake
