array initialization on separate file in verilog

hello...

can i initialize array in separate file n use it in another file..

like in file (define.v)

a[0]=1;

a[1]=2;

want to use this definition in another file (main.v)

module

input in;

output etc etc;

reg [1:0] a[0:1];

`include "define.v"

endmodule

but its nt working...

help!!!