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Altera_Forum
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16 years ago

array initialization on separate file in verilog

hello... can i initialize array in separate file n use it in another file.. like in file (define.v) a[0]=1; a[1]=2; want to use this definition in another file (main.v) ...
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Altera_Forum
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16 years ago

You can use the "`include" to accomplish what you are trying to accomplish. However, you need to read the following coding guidelines on how to initialize memory:

http://www.altera.com/literature/hb/qts/qts_qii51007.pdf

Read the section "Specifying Initial Memory Contents at Power-Up" starting on page 6-27

Jake