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Altera_Forum
Honored Contributor
15 years agoHi PeterCH,
thanks for the rapid answer. I don't see a reset_n in my design. And I have some pins you didn't mention: gxb_powerdown_pcie_compiler_0 and pll_powerdown_pcie_compiler_0 (inputs) and rate_ext_pcie_compiler_0 and clock outputs (output). I'm using Quartus 10.0 . Don't you see this signals? Should I try Quartus 9.1 rather than the new version? My clock was connected to F18(p) and F17(n). I will test your locations. Regards, Frederik