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Did you constrain all timing paths? Verify this with Processing --> Start --> Start Classic Timing Analyzer Constraint Check.
Do you have reported timing violations? If so, those could cause problems in hardware even if timing simulation works.
Even if you correctly constrained all paths and have no reported timing violations, the ripple and gated clocks can cause problems. See my posts at
http://www.alteraforum.com/forum/showthread.php?t=754.
Your I2C problem might be caused by something else, but you need to be careful with the ripple and gated clocks anyway.
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Thanks for you help, but I constrained all the timing paths(No warnings/Errors in constraint check). I also don't get any timing violations.
I0m using the atufm Megafunction so I cannot avoid gated/rippled clocks. I'm assuming that altera checked that Megafunction. I'll read your post in detail tomorrow. Thanks a lot anyways.
(And its not a chip failure, tried it on several hardware)
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